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And on their own, they don’t generally add value to the feature set offered by that SmartNIC. Beyond architectural sketches, we won’t call out these control-plane Arm cores below, as they’re required plumbing. They don’t touch any of the network packets, and they often run “out-of-band,” meaning that they can’t be accessed via “normal” network interfaces or PCIe commands.Īlso, the cores should only accept duly signed firmware bundles over previously secured interfaces.
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These Arm cores typically handle loading code into the other processing elements, gathering statistics and logs, and watching over the health and configuration of the SmartNIC. Some even allow for loading a modified Linux kernel into one or more of these cores. Many of these SmartNICs will often use one or more Arm cores for control-plane management within the NIC.
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The capability to load future code into a NIC, making it a SmartNIC, requires additional computational power and onboard memory not found in generic NICs.